ONE TRANSISTOR GATE CIRCUITS CRACK

Wafer-scale integration of double gated WS 2-transistors in 300 mm Si CMOS fab. High-mobility three-atom-thick semiconducting films with wafer-scale homogeneity. Large-scale flexible and transparent electronics based on monolayer molybdenum disulfide field-effect transistors. Wafer-scale growth and transfer of highly-oriented monolayer MoS 2 continuous films.

ONE TRANSISTOR GATE CIRCUITS CRACK

Controlled crack propagation for atomic precision handling of wafer-scale two-dimensional materials. Two-dimensional transition metal dichalcogenides as atomically thin semiconductors: opportunities and challenges. Uniform and ultrathin high- κ gate dielectrics for two-dimensional electronic devices. A library of atomically thin metal chalcogenides. MoS 2 transistors with 1-nanometer gate lengths. Two-dimensional materials for next-generation computing technologies. Two-dimensional semiconductors for transistors.

Promises and prospects of two-dimensional transistors. Multi-terminal memtransistors from polycrystalline monolayer molybdenum disulfide. Gate-tunable memristive phenomena mediated by grain boundaries in single-layer MoS 2. This scalable van der Waals integration method may be useful for reliable integration of 2D semiconductors with mature industry technology, facilitating the technological transition of 2D semiconductor electronics. The approach is further used to create various logic gates and circuits, including inverters with a voltage gain of up to 585, and logic OR gates, NAND gates, AND gates and half-adder circuits. The van-der-Waals-contacted devices display an atomically clean interface with much smaller threshold variation, higher on-current, smaller off-current, larger on/off ratio and smaller subthreshold swing than those fabricated with conventional lithography. Our scalable van der Waals integration process allows damage-free integration of high-quality contacts on monolayer MoS 2 at the wafer scale and enables high-performance 2D transistors. By designing a quartz/polydimethylsiloxane semirigid stamp and adapting a standard photolithography mask-aligner for the van der Waals integration process, our strategy ensures a uniform mechanical force and a bubble-free wrinkle-free interface during the pickup/release process, which is crucial for robust van der Waals integration over a large area. Here we demonstrate a highly reproducible van der Waals integration process for wafer-scale fabrication of high-performance transistors and logic circuits from monolayer MoS 2 grown by chemical vapour deposition. However, the fabrication of 2D transistors using traditional lithography or deposition processes often causes undesired damage and contamination to the atomically thin lattices, partially degrading the device performance and leading to large variation between devices. Two-dimensional (2D) semiconductors such as molybdenum disulfide (MoS 2) have attracted tremendous interest for transistor applications.

One transistor gate circuits